In the semiconductor device manufacturing process, etching is carried out without exception. For example, in the case of manufacturing a field-effect transistor as a semiconductor device, an insulating film such as a silicon oxide film being a material of an interlayer insulating film is formed with contact holes by reactive ion etching upon carrying out wiring to a source and a drain, and electrodes or metal wires are applied to such opened contact holes.
In this case, the contact resistance at the bottom of the contact hole increases in inverse proportion to the contact diameter if the resistivity of the underlying silicon is constant. Accordingly, as the miniaturization and integration of a semiconductor device advance more and more so that the contact diameter is further reduced, the resistivity at the contact bottom tends to increase. Particularly, in the case of forming a contact hole by normal reactive ion etching, the underlying silicon is subjected to damage when the underlying silicon is exposed upon completion of the etching of an oxide film. This is because high-energy ions are irradiated onto the underlying silicon and, as a result, impurities such as boron or phosphorus doped in the silicon are inactivated so that the resistivity of the underlying silicon increases. Particularly, since boron serving as impurities for forming a p+ layer has dangling bonds, it tends to be inactivated much more easily as compared with phosphorus or arsenic. Therefore, if this p+ layer is subjected to ion irradiation, it nearly becomes a p layer due to the inactivation. As a consequence, the resistivity of the underlying silicon increases.
In order to prevent the increase in resistivity of the underlying silicon due to the ion irradiation as described above, proposal has been made of a method of introducing a damage removal process after the etching. This method is a technique that, after contact hole etching and a resist removal process, removes by chemical dry etching a damaged layer in which carriers are inactivated, carries out ion implantation for doping impurities at high concentration again, and further carries out activation annealing.
Further, as another conventional technique for solving a problem following the increase in resistivity, damage-free two-step etching is proposed, for example, in “The Ninth International Symposium on Semiconductor Manufacturing, Proceeding of ISSM2000, pp. 102-105, Tokyo, Sep. 2000.” (hereinafter referred to as Prior Art 1). According to this technique, in order to reduce ion irradiation damage to the underlying silicon and further not to increase an etching time, etching is carried out by setting a self-bias voltage (Vdc) to −500V to −600V for 90% of a contact hole while etching is carried out by setting Vdc=−150V for the remaining 10% of the contact hole. In this event, an introducing gas for use in plasma excitation is Xe, C4F8, CO, or O2.